A Parallel-Pipelined Constant Geometry Algorithm (PCGA) for Computation of FFT on a Special Processor

In digital signal processing applications, we usually use DFT (discrete Fourier transform) to transfer signal from time-domain to frequency-domain. In past decades, there were many papers discussing and exploiting FFT (fast Fourier transform) architectures for hardware implementation. In this paper, we proposed a novel VLSI FFT processor based on parallel-pipelined constant geometry algorithm (PCGA). This processor provides constant geometry for each stage of FFT, data reordering is not needed any more. Besides, the architecture of PCGA FFT processor is simple and regular, and the PCGA FFT processor always needs two-set of data RAM which acts as data storages for reading and writing data alternately. Especially, the PCGA FFT processor increases throughput with increasing input points, and sufficiently exploits the advantage of parallel-pipelined computation for digital signal processing applications. Hence, comparing to conventional FFT processors, the PCGA FFT processor is more suitable and efficient for processing large number-point FFT. A novel implementation of the FFT processor should be achieved.